IC Validator Fusion Demo: Explorer DRC and Heatmap in Fusion Compiler / IC Compiler II
2:47
Learn how to isolate key design weaknesses in early design planning and P&R stages using Explorer DRC. DRC Violation heat map to highlight a sampling of DRC across the design
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Play video IC Validator PERC VUE Demo – Part 1
IC Validator PERC VUE Demo – Part 1
In part 1-7 part series, we describe port & switch setup using the esd_setup.rs file & demonstrate how to setup a Synopsys IC Validator PERC run using the example script found in the Synopsys IC Validator installment directory.
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Play video 03- How to run IC Validator LIVE DRC Tool using IC Compiler II GUI
03- How to run IC Validator LIVE DRC Tool using IC Compiler II GUI
IC Validator Live DRC is an interactive DRC engine to get immediate DRC feedback while doing physical implementation. In this video learn how to use Live DRC in IC Compiler II and Fusion Compiler to run DRC on-the-fly and debug DRC results quickly.
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Play video IC Validator Dynamic Resource Allocation For Efficient Compute Resource Usage
IC Validator Dynamic Resource Allocation For Efficient Compute Resource Usage
The IC Validator elastic CPU feature dynamically allocates resources during an IC Validator run. The host_elastic command automatically manages resources by adding/removing hosts as per run requirement and optimizes compute resource CPU utilization.
3:13
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Play video IC Validator PERC VUE Demo – Part 3
IC Validator PERC VUE Demo – Part 3
Overview of debugging a Topology based run with ICV PERC.
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Play video IC Validator PERC - Comprehensive Reliability Verification
IC Validator PERC - Comprehensive Reliability Verification
IC Validator PERC is a comprehensive robust solution for verification of reliability and ESD of modern designs. IC Validator PERC enables designers to do a broad set of complex reliability verification checks at cell, block and full chip level.
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Play video IC Validator Workbench: Overview
IC Validator Workbench: Overview
Learn about IC Validator Workbench, a high performance hierarchical layout viewing and analysis tool. It is a companion layout analysis toll for IC Validator physical verification solution.
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