IC Validator PERC VUE Demo -Part 4
6:08
Overview of debugging a Current Density run using ICV PERC VUE.
Related Videos
In IC Validator Demos
-
Play video IC Validator PERC VUE Demo – Part 3
IC Validator PERC VUE Demo – Part 3
Overview of debugging a Topology based run with ICV PERC.
2:30
-
Play video IC Validator PERC VUE Demo - Part 5
IC Validator PERC VUE Demo - Part 5
Overview of debugging a Point-to-Point Resistance run using ICV PERC VUE.
6:31
-
Play video IC Validator PERC - Comprehensive Reliability Verification
IC Validator PERC - Comprehensive Reliability Verification
IC Validator PERC is a comprehensive robust solution for verification of reliability and ESD of modern designs. IC Validator PERC enables designers to do a broad set of complex reliability verification checks at cell, block and full chip level.
3:11
-
Play video ICV PERC VUE Introduction - Topology Results
ICV PERC VUE Introduction - Topology Results
Overview of debugging a Topology based run with ICV PERC.
2:59
-
Play video IC Validator Dynamic Resource Allocation For Efficient Compute Resource Usage
IC Validator Dynamic Resource Allocation For Efficient Compute Resource Usage
The IC Validator elastic CPU feature dynamically allocates resources during an IC Validator run. The host_elastic command automatically manages resources by adding/removing hosts as per run requirement and optimizes compute resource CPU utilization.
3:13
-
Play video IC Validator Workbench: Overview
IC Validator Workbench: Overview
Learn about IC Validator Workbench, a high performance hierarchical layout viewing and analysis tool. It is a companion layout analysis toll for IC Validator physical verification solution.
3:25