IC Validator PERC VUE Demo - Part 5
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Overview of debugging a Point-to-Point Resistance run using ICV PERC VUE.
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Overview of debugging a Point-to-Point Resistance run using ICV PERC VUE.
IC Validator Live DRC is an interactive DRC engine to get immediate DRC feedback while doing layout design. In this video learn how to use Live DRC in custom compiler to run DRC on-the-fly in custom compiler and debug DRC results quickly.
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IC Validator PERC is a comprehensive robust solution for verification of reliability and ESD of modern designs. IC Validator PERC enables designers to do a broad set of complex reliability verification checks at cell, block and full chip level.
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Overview of debugging a Topology based run with ICV PERC.
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The IC Validator elastic CPU feature dynamically allocates resources during an IC Validator run. The host_elastic command automatically manages resources by adding/removing hosts as per run requirement and optimizes compute resource CPU utilization.
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Learn about IC Validator Workbench, a high performance hierarchical layout viewing and analysis tool. It is a companion layout analysis toll for IC Validator physical verification solution.
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Overview of debugging a Current Density run using ICV PERC VUE.
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